A 3-bit binary number's two's complement calculator, functioning by first inverting all bits and then adding one. Implement this addition through a series of three cascaded 1-bit half-adders. Sketch a logic diagram showing these half-adders at block level, and construct a Verilog module at the gate level utilizing instances of the half-adder module developed previously. Apply Verilog vectors for handling multi-bit variables for both inputs and outputs. Thoroughly test the circuit with all possible input permutations and record the outcomes in both binary and signed decimal notation.