a) Present a realization of f and g using only two-input NAND gates. With the only rule of not using NAND as NOT use the distributive and exchange properties. The number of gates is also given. You can assume that the inputs are available both normal and complemented.
b) Check your result for f using the ISE and the FPGA to do so by first creating a schematic symbol
that produces the inputs a, b, c, _a, _b and _c. This symbol provides both the normal and complementary inputs available for testing.
and complemented inputs available for testing.

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a) Present a realization of f and g using only two-input NAND gates. With the only rule of not using NAND as NOT use the distributive and exchange properties. The number of gates is also given. You can assume that the inputs are available both normal and complemented.

b) Check your result for f using the ISE and the FPGA to do so by first creating a schematic symbol
that produces the inputs a, b, c, _a, _b and _c. This symbol provides both the normal and complementary inputs available for testing.
and complemented inputs available for testing.

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