(Solved): any help please In this project students are asked to implement a an XTEA Encryption/Decryption VHDL ...

In this project students are asked to implement a an XTEA Encryption/Decryption VHDL Engine, implemented in both C code and VHDL code. It supposed to be built as a custom hardware module and be interfaced to the NIOS II soft processor in the AlterIntel Cyclone V FPGA chip [De-10Nano board]. The HDL code implements 2 number of pins: first an input from stdr_logic_vector type form of 32-bit length, and second an output with 32-bit of the same type. The Key is 32-bit in length, and they must be stored inside the VHDL code. The input reception and output generation may take multiple clock cycles or states but could be designed in less than that if was applicable. The internet could be surfed to lookup codes for both C and VHDL but the group is responsible to convert and modify the code to the required form. It is important to convert the floating-point format of the coefficients to an integer format and other operations such as multiplication and addition must consider this conversion process as well. It is required from the group to do the following 1- Develop the C and the VHDL code, to be run both in NIOS II. 2- Test the VHDL code in ModelSim using testbench. The student is required to develop the testbench VHDL code. Also, to generate a run with arbitrary values for inputs for testing purpose. 3- Use the Quartus beside the Platform (Qsys) applications to develop the Nios II processor and the custom XTEA hardware accelerator interfaced together. 4- Measure comparatively the time it takes to compute a 32rounds of XTEA encryption in both the software besides the hardware. 5- Finish the report Introduction to Extended Tiny Encryption Algorithm Cryptography The Tiny Encryption Algorithm (TEA) was introduced by David Wheeler and Roger Needham in '94. Their main design goal was to produce a cipher that is simple, short and does not rely on large tables or pre-computations. Shortly after TEA was published, a few minor weaknesses were found. The original authors eliminated those weaknesses in a new version of TEA called XTEA for extended TEA. The main routine requires two fewer addition operations which results in a faster algorithm. TEA uses only simple addition, XOR and shifts, and has a very small code size. This makes TEA an ideal candidate to provide data security services for wireless sensor network (WSN) nodes which have limited memory and computational power. The Extended Tiny Encryption Algorithm (XTEA) is a block cipher that uses a cryptographic key of 128 bits to encrypt or decrypt data in blocks of 64 bits. Each input block is split into two halves $$y$$ and $$z$$ which are then applied to a routine similar to a Feistel network for $$\mathrm{N}$$ rounds where $$\mathrm{N}$$ is typically 32. Most Feistel networks apply the result of a mixing function to one half of the data using XOR as a reversible function. XTEA uses for the same purpose integer addition during encryption and subtraction during decryption. Figure 1 shows the $$\mathbf{C}$$ source code for XTEA. Additional parentheses were added to clarify the precedence of the operators. The main variables $$y,z$$, and sum, which assists with the subkey generation, have a length of 32 bits. All additions and subtractions within XTEA are modulo $$2^{32}$$. Logical left shifts of $$z$$ by 4 bits are denoted as $$z?4$$ and logical right shift by 5 bits as $$z>>5$$. The bitwise XOR function is denoted as " $$?"$$ in the source code and $$?$$ in this writing. Fig. 1. Source code of XTEA The first part of the algorithm is the eneryption routine, and the second part is the decryption routine. The while-loop constitutes the round function. The formulae that compute the new values for $$y$$ and $$z$$ can be split into a permutation function $$f(z)=(z?4?z>>5)+z$$ and a subkey generation function sum $$+k$$ (sum). The function $$k$$ (sum) selects one block out of the four 32-bit blocks that comprise the key, depending on either bit 1 and 0 or bits 12 and 11 of sum. The results of the permutation function and the subkey generation function are XORed and then applied to $$y$$ and $$z$$ respectively, by addition in the case of encryption or subtraction in the case of decryption. Operation of the code: Send 32-bit data to the VHDL engine from the Nios-Il soft processor. The engine makes the appropriate operations to the samples then produce a single output that is returned to the Nios-II. (See Lab-4 and Chapter-20 in Pong's book for more information) The code must incorporate timing measurements quite capable of measuring the time elapsed from start to end (See Lab-4 and Chapter-20 in Pong's book for more information). This should be done both in hardware and software operations taken by the NIOS-II