c. Verilog Theory ( 40 points): a. Define always statement in Verilog ? Give examples for usage in test benches and design files ( ( mathbf{1 0} ) points) b. Differentiate between reg and wire ( ( mathbf{1 0} ) points) c. List atleast 2 differences between task and function. Give appropriate examples ( ( mathbf{1 0} ) points) d. What is t

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c. Verilog Theory ( 40 points): a. Define always statement in Verilog ? Give examples for usage in test benches and design files (  (  mathbf{1 0}  ) points) b. Differentiate between reg and wire (  (  mathbf{1 0}  ) points) c. List atleast 2 differences between task and function. Give appropriate examples (  (  mathbf{1 0}  ) points) d. What is the difference between  $monitor and  $display? Explain it using Verilog testbench statements. (  (  mathbf{1 0}  ) points)

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