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(Solved): Consider a setup very similar to HW#1 Question 2. The latencies and code are below for your referenc ...



Consider a setup very similar to HW#1 Question 2. The latencies and code are below for your reference (note a slight change in the code compared to HW1Q2: the mult and div are reordered). This time let’s consider how dynamic scheduling might help. Assume a microarchitecture as shown below. Assume that the ALUs can do all arithmetic operations (fmul.d, fdiv.d, fadd.d, addi, sub) and branches, and that the Reservation Station (RS) can dispatch for execution, at most, one operation to each functional unit per cycle (one op to each ALU plus one memory op to the load/store unit). Assume there are sufficient reservation station entries to hold all instructions in the code snippet.



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