Consider an instruction pipeline with five stages without any branch prediction. The stage delays for each stage are 5 n sec, 6 n sec, 10 n sec, 8 n sec and 6 n sec, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 n sec. A program consisting of 12 instructions 1 thru 12 is executed in the pipelined processor. Instruction 3 is the only branch instruction, and its branch target is 8. If the branch is taken during the execution of this program, what is the time needed to complete the program. Draw the pipeline diagram to show clock cycles with time.
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