Design Verilog RTL module to detect both rising and falling edges on the input and write the testbench to cover two pulses of "signal_in " as follows.

1. Design Verilog RTL module to detect both rising and falling edges on the input and write the testbench to cover two pulses of "signal in" as follows. module Det (clk signal in out); $input input outplt //Your code clk; signalin: out;$

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Design Verilog RTL module to detect both rising and falling edges on the input and write the testbench to cover two pulses of "signal_in " as follows.

1. Design Verilog RTL module to detect both rising and falling edges on the input and write the testbench to cover two pulses

1. Design Verilog RTL module to detect both rising and falling edges on the input and write the testbench to cover two pulses of "signal in" as follows. module Det (clk signal in out);

input input outplt //Your code clk; signalin: out;

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