(Solved): Example of state diagram Design a synchronous counter that continuously counts in the follow ...

Design a synchronous counter that continuously counts in the following sequence: $\{001,010,100\}$. - The counter has an asynchronous input reset that places the state into the state associated with cnt $=$ "001". The counter has a hold input $(\mathrm{H})$ that prevent the counter from changing states When $\mathrm{H}$ is asserted, the cnt output is " 000 "; otherwise the count is one of the three values in the count sequence. - Make the counter self-correcting by directing all unused states to the state associated with the "010" count. The cnt output in any illegal state should be "000". Do the following: 1. Provide a PS/NS table that includes the outputs 2. Provide a state diagram describing your FSM 3. Minimize the width of the state registers