(Solved): \[ f=x_{1} x_{2} \overline{x_{4}}+x_{1} \overline{x_{2}} x_{3}+x_{2} x_{3} \overline{x_{4}} \] Equ ...

\[ f=x_{1} x_{2} \overline{x_{4}}+x_{1} \overline{x_{2}} x_{3}+x_{2} x_{3} \overline{x_{4}} \] Equivalent resistor for all NMOS transistors: \( R_{N}=4.7 \mathrm{k} \Omega \) Equivalent resistor for all PMOS transistors: \( R_{P}=2.6 \mathrm{k} \Omega \) Implement \( \boldsymbol{f} \) with "a CMOS Logic Circuit", "an NMOS Pass Transistor Logic Circuit", and "a Dynamic Logic Circuit". For pass transistor logic select an ordering of \( x_{4}, x_{3}, x_{2} \), and \( \boldsymbol{x}_{\mathbf{1}} \). There should be total of three circuits/implementations. SIMULATION: Construct each of the three circuits implemented using SPICE. Select \( V_{D D}=5 \mathrm{~V} \) (logic 1) and ground \( =0 \mathrm{~V} \) (logic 0 ) for inputs. Connect body terminals of NMOS and PMOS transistor to \( 0 \mathrm{~V} \) and \( 5 \mathrm{~V} \), respectively. Select \( \mathrm{W}_{\mathrm{P}}=2 \mathrm{u}, \mathrm{L}_{\mathrm{P}}=1 \mathrm{u} \) for all \( \mathrm{PMOS}^{\mathrm{T}} \) transistors; select \( \mathrm{W}_{\mathrm{N}}=1 \mathrm{u}, \mathrm{L}_{\mathrm{N}}=1 \mathrm{u} \) for all NMOS transistors. Use T15DN and T15DP spice models for NMOS and PMOS transistors, respectively a) Statically test your implementations by applying two cases \( x_{1}=1, x_{2}=\mathbf{0}, x_{3}=1, x_{4}=1 \), and \( x_{1}=\mathbf{0}, x_{2}=\mathbf{1}, x_{3}=\mathbf{0}, x_{4}=\mathbf{1} \). For each case sketch Vout in time domain. There should be total of 6 Spice figures. b) Connect a load capacitor of \( 10 \mathrm{pF} \) to the output of each circuit. Apply square pulse waves with frequency of \( 10 \mathrm{kHz} \) to required inputs. Find the worst case propagation delays tPLH and tpHL, by sketching VIN \& Vout in time domain, for each implementation. There should be total of \( \mathbf{6} \) delay values and Spice figures.