(I'll add the picture to the comment)!!! <3
A basic computer design is given in the figure above. Every register has Ld(load) CLR(clear) and INC(increment) control outputs. The memory(Bellek) has its read and write control inputs.
Selection bits S0,S1 are responsible for writing to BUS1
S1 S0
0 0-> Write R1 to BUS1
0 1-> write R2 to BUS1
1 0-> BUS2 to BUS1
------
Selection bits S3,S2 are responsible for writing to BUS2
S3 S2
0 0-> Write Memory to BUS2
0 1-> write R3 to BUS2
1 0-> Write R4 to BUS2
1 1 -> BUS1 to BUS2
---------------------
Selection bits S5,S4 are responsible for ALU operations
S5 S4
0 0-> R1<--R2
0 1-> R1<--R1+R2
1 0-> R1<--R1- R2
1 1-> R1<--R2 And (v) R1
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According to this computer what is the RTL commands(in order) that must be perform to this operation and how many clock pulse are required?
Opr1 : R1<-- R4 + M[R3+R1]
RTL ??? Clock pulses??
Opr2: R4<-- R2 - R3
RTL ?? Clock pulses??