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(Solved): verilog HDL code | VLSI Write an HDL code for the following specifications. Write a linea ...
verilog HDL code | VLSI
Write an HDL code for the following specifications. Write a linear testbench to verify the design. Input: clk, reset_n, A, B Output: AEQB, AGTB, ALTB The block has an active low asynchronous reset and works on the posedge of clock. The block takes two 4 bit numbers A,B and compares them. There are 3 single bit outputs and they are 1 in the following conditions otherwise 0. 1401 AEQB i.e. A equals B AGTB i.e. A greater than B ALTB i.e. A less than B
Expert Answer
Verilog HDL code for the module: module random_block( clk, reset_n, A, B, AEQB, AGTB, ALTB); input clk; input reset_n; input [3:0] A; input [3:0] B; output reg AEQB; output reg AGTB; output reg ALTB; always @(posedge clk) beg