Our CPU is pipelined, with the register write of instructions completing 3 clocks after instructions is fetched In such a pipeline, which instruction number in the sequence of instructions shown below (fetched in consecutive clocks), is the first to have a data hazard with a preceding instruction. Enter the -1 if there is no such hazard. Reminder: Left-most field in these instructions are the destination register. 0: mull $S0, $S0, $S2 1: add $S5, $S1, $S2 2: add $S2, $S1, $S0 3: mull $S5, $S0, $S4 4: add $S1, $S1, $S2 5: mull $S6, $S3, $S4 6: add $S1, $S5, $S4