Problem 1 (65%)
a) What are Dependency and Hazard in a pipeline processor architecture?
b) What are the different types of Hazards?
c) What is forwarding technique? What are the different forwarding methods? What are types of hazards are mitigated by forwarding and how?
d) For the following RISC V instructions, identify dependencies and hazards. For hazards, identify the types of hazards (EX or MEM).
lw sp, 20(ra)
and tp, sp, t0
or s0, sp, t1
add s1, tp, t0
beq s0, s1, label
e) For the above code block, determine the number of clock cycles (CC) for processor with (i) no forwarding and (ii) with forwarding.
f) Can you rewrite the above code for a processor with forwarding to reduce CC even further? Explain.
Problem 2 (35%)
a) What are Hit Rate (HR) and Miss Penalty (MP)?
b) Define: Compulsory miss, Capacity miss, Conflict miss.
c) For a direct mapped cache of 8 spaces of 1-word width each, if the access requests are as follows, determine Hit (H) or Miss (M) for each access, and show corresponding index and tag in a tabular format. Assume 8-bit addresses including Byte offset.
Address (8-bit with Byte offset) access requests (in sequence)
01011000
01101000
01011000
00100000
00001100
00101000
00111000
00100000
01101000
00101000
00001100
01011000