Problem 2. The circuit shown in Figure 2 is used as a bias circuit in analog CMOS integrated circuits. Instead of resistors, nMOS transistors with properly sized (W/L) ratios are used to achieve bias voltages of 1V and 3V from a 5V supply. The enhancement-mode nMOS transistors have the following parameters; VTN=0.5V,knn=200A/V2=0

Question

Problem 2. The circuit shown in Figure 2 is used as a bias circuit in analog CMOS integrated circuits. Instead of resistors, nMOS transistors with properly sized (W/L) ratios are used to achieve bias voltages of

1 V

and

3 V

from a

5 V

supply. The enhancement-mode nMOS transistors have the following parameters;

V_{TN} = 0.5 V, kn_{n} = 200 μ A / V^{2} γ = 0, λ = 0

. The current that flows through the transistors is

20 μ A

as shown in the figure. Determine the (W/L) ratios of

Q_{1}, Q_{2}

, and

Q_{3}

so that

1 V

and

3 V

bias voltages as shown in the figure are established.

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