Refer to the diagram above for this question. The flip-flop FF2 has a setup time requirement of 150 psec. The clock tree buffers between point A and
B
have a total delay of 300 psec. The combinatorial block between point
C
and
D
has a total delay of 1.5 nsec. If the positive clock edge is launched from point
A
at time
T=2nsec
, what is the latest time the data must be available at point C (the output of FF1), in order to meet the setup time of FF2.
T=150psec
T=650
psec
T=800psec
T=900psec