(Solved): the Serial Adder was analyzed as a FSM. You will now use theSerial Adder as a component of a larger ...

the Serial Adder was analyzed as a FSM. You will now use the Serial Adder as a component of a larger system, the Bit Serial Adder with Accumulator as shown in Figure 1.

The Bit Serial Adder with Accumulator will include the following components: 

• Control FSM - This is the main control unit of the Bit Serial Adder with Accumulator 

• Accumulator - The 4-bit Accumulator register has two functions: (i) Is loaded with one of the adder operand 'x'; (ii) Contains the final addition result 

• Added Register - This 4-bit register is loaded with adder operand 'y' 

• Serial Adder - This 1-bit adder serially adds individual bits of operands 'x' and 'y'

 

The following signals, some shown in Figure 1, must be used in your design: 

• Clock - The system clock signal 

• Reset - Although not shown, the system must include an active high reset signal to reset the FSM state Flip-Flops, X and Y Flip-Flops, and Serial Adder state Flip-Flop to logic 0. 

• N - Also known as 'Start', this active high signal starts the Bit Serial Adder addition operation 

• Sh - Also known as 'Shift', this active high signal causes the Accumulator and Added Register to serially shift on a clock edge 

• Done - This active high signal indicates the Bit Serial 4-bit addition is complete 

• Xin - This active high 4-bit signal is the X operand input to the Bit Serial Adder 'X' register; note that 'X' register is also the Accumulator 

• Xout - This active high 4-bit signal is the X operand output signal from the Bit Serial Adder; note that 'X' register is also the Accumulator 

• Yin - This active high 4-bit signal is the Y operand input to the Bit Serial Adder 'Y' register 

• Yout - This active high 4-bit signal is the Y operand output signal from the Bit Serial Adder

1. Create draft timing diagrams to identify system operation, unknowns and conflicts
2. Create Control FSM State Diagram
3. Create Control FSM State Table
4. Create Control FSM State Assignment Table
5. Create K-Maps for:
a. Next State Signals
b. Output Signals
6. Design & Simulate Final Control FSM Schematic
7. Design & Simulate Bit Serial Adder Component Schematics
8. Design & Simulate Bit Serial Adder Full Design Schematic
 

Accumulator MA Xi N (Start Signal) Sh X3 X X X sumi Full Adder Sh Yi Control Circuit Y3y2 y, yo Addend Register si Ge1 Clock Serial Adder IQ D+ OCK Sh Clock Control FSM Done Ci 0 1 Bit Serial Adder with Accumulator sumi Cit 1 0 1 0 1 to 0101 0111 ti J0010 1011 t2 0001 1101 t3 1000 1110 t4 1100 0111 1 1 1 1 1 (1) 0 (0) 0 Figure 1: Bit Serial Adder with Accumulator Block Diagram