The VHDL code should use port mapping to ensure that the circuit created from code (if viewed in the RTL viewer in Quartus) is similar to the circuit shown in fig A.2 make sure to implement the circuits as shown in the fig A.2 (aside from changing the 1 an enable input use component and port mapping without using arithmetic and unsigned to achie

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The VHDL code should use port mapping to ensure that the circuit created from code (if viewed in the RTL viewer in Quartus) is similar to the circuit shown in fig A.2  make sure to implement the circuits as shown in the fig A.2 (aside from changing the 1 an enable input   use component and port mapping without using arithmetic and unsigned to achieve this.

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