(Solved): We want to build a NAND gate circuit to compute the parity of an n-bit number. The parity is define ...

We want to build a NAND gate circuit to compute the parity of an n-bit number. The parity is defined as 1 if and only if there are an odd number of 1's in the number. One way of doing this is to build the circuit 1 bit at a time (as in the adder), such that the circuit computes the parity after that bit as a function of the parity up to that bit and the one input bit. A block diagram of the first few bits of such a circuit is shown below ( 20 points). a. Show a NAND gate circuit to implement 1 bit and compute the delay for $n$ bits. Assume that inputs are available only uncomplemented (complemented one needs to use logic gates to implement, for example, a' can be implemented with one NAND gate). b. Reduce the delay by implementing 2 bits at a time.